September 7, 2017 - Half day workshop
Embedding Passive and Active Components: PCB Design and Assembly Process Fundamentals
Date: Thursday September 7, 2017
Time: 8.30 am registration for 9.00 start Finish 12.15 pm
REGISTRATION CODE: VS2
Both uncased active and passive component elements are candidates for embedding but the decision to embed components within the multilayer circuit structure must be made early in the design process. Although the printed circuit has traditionally served as the platform for mounting and interconnecting active and passive components on the outer surfaces, companies attempting to improve functionality and minimize space are now considering embedding a broad range of components within the circuit structure.
Some components are easy candidates for integrating into the substrate while others may involve more complex processes and will be difficult to rationalize. Although a majority of the discrete passive and active devices may remain mounted on the outer surfaces of the multi-layer board, embedding one or more silicon based semiconductor elements within the inner layers of the structure will enable greater utilization of the circuit boards outer surfaces. Benefits can include improved performance, For example, by embedding the semiconductor on an inner layer of the circuit directly in line with a related semiconductor package mounted on the outer surface, the conductor interface can be minimized. The close coupling of semiconductor elements significantly reduces inductance and contributes to increasing signal speed.
This course was developed to better enable the product designer and manufacturing specialist to have a clear understanding of the principles for embedding components in an organic multilayer circuit board structure. The tutorial will include design guidelines, material selection and termination methodology for embedding active and passive (resistor, capacitor, inductor and discrete transistor) elements. Several process variations for embedding and interconnecting thinned semiconductor elements within the multi-layer PCB will be illustrated with examples of both core type and coreless substrate structures.
Who Should Attend:
The material has been developed specifically for PCB Designers, Design Engineers and those responsible for electronic product development, assembly processing and manufacturing efficiency. This would include manufacturing and test engineering specialists for the OEM, ODM and EMS providers.
Vern Solberg is a technical consultant specializing in SMT and microelectronics design and manufacturing technology. He has served the electronics industry for more than thirty years in areas related to both commercial and aerospace electronic product development and is active as an author and educator. Mr Solberg holds several patents for IC packaging innovations including the multiple die and folded-flex 3D package technology and is the author of Design Guidelines for Surface Mount and Fine-Pitch Technology a McGraw-Hill publication. Mr Solberg's last visit to Australia was received with great acclaim by all who attended and we are delighted he is able to again participate at the SMCBA conference.
Mr. Solberg has been involved with the training of both students and faculty members at the University of Wisconsin, School of Engineering in Milwaukee and Kansas State Universities Microelectronic Laboratory in Salina. He also participates in and supports several industry organizations including SMTA, IEEE, IMAPS and IPC developing electronic industry related standards. Vern is also a member of the IPC organizations Ambassadors Council as well as a Certified IPC Trainer for IPC-A-600 and IPC-A-610.
Current IPC standards development activity-
- Chairman- IPC-7094, ‘Design and Assembly Process Implementation for Flip Chip and Die Size Components’
- Co-chair- IPC-7093, ‘Design and Assembly Process Implementation for Bottom Terminal Components (SON and QFN)’.
- Co-chair- IPC-7092, ‘Design and Assembly Process Implementation for Embedded Components’.
- Co-chair- IPC-7091, ‘Design and Assembly Process Implementation for 3D Semiconductor Package Technology’