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September 7, 2017 - Half day workshop

Design and Assembly Process Implementation for Flip-Chip, Wafer Level and 3D Semiconductor Package Technologies

Date: Thursday September 7, 2017

Time: 1.15pm registration for 1.30 pm start   Finish 4.30 pm approx

REGISTRATION CODE:  VS3

In order to better meet their performance and miniaturization goals manufacturers are looking for higher functionality for their semiconductor packages. For that reason, many manufacturers will rely heavily on more innovative system-level IC package solutions, solutions for integrating a number of already proven functional elements within a single-package outline. This capability has been stimulated by the rapid deployment of new products from a growing number of competing companies’ where time-to-market can be the difference between leading and following.

This half-day course addresses the design and assembly challenges for developing and implementing flip-chip and multiple function System-in-Package (SiP) technology. Although integrating several semiconductor functions onto a single die element (System-on-Chip) appears to provide a viable solution for some, development cost and time has often proved to be excessive. On the other hand, many companies have realized that wafer level packaging (WLP) and integrating mature multiple-die elements into a 2D or 3D configured package actually proves to be superior to the multiple function die concepts because it minimizes risk, significantly reduces development time and cost.

The focus of the presentation material is on design and assembly methodology:

  1. Market Drivers for System Level Integration and Miniaturization
  2. Evolution of Flip-Chip, WLP, 2D and 3D Multiple Die Packaging
  3. Exploring Advanced 3D Semiconductor Package Innovations
  4. Organic and Inorganic Package Level Substrate Fabrication
  5. 2D, 2.5D and 3D Package Assembly Process Methodologies

Course objectives -

The material presented has been developed to better enable the product designer and manufacturing specialist to evaluate a broad number of semiconductor packaging methodologies. The examples shown will furnish both physical and monetary benefits gained using multiple die packaging as well adverse concerns related to supply-chain obstacles and infrastructure limitations.

Who should attend -

This course will benefit PCB Designers, Design Engineers and those responsible for semiconductor package and electronic product development, assembly processing and manufacturing efficiency as well as manufacturing and test engineering specialists for the OEM, ODM, EMS and OSATs (Outsourced Assembly and Test) providers.

The Presenter:

Vern Solberg is a technical consultant specializing in SMT and microelectronics design and manufacturing technology. He has served the electronics industry for more than thirty years in areas related to both commercial and aerospace electronic product development and is active as an author and educator. Mr Solberg holds several patents for IC packaging innovations including the multiple die and folded-flex 3D package technology and is the author of Design Guidelines for Surface Mount and Fine-Pitch Technology a McGraw-Hill publication.  Mr Solberg's last visit to Australia was received with great acclaim by all who attended and we are delighted he is able to again participate at the SMCBA conference.

Mr. Solberg has been involved with the training of both students and faculty members at the University of Wisconsin, School of Engineering in Milwaukee and Kansas State Universities Microelectronic Laboratory in Salina. He also participates in and supports several industry organizations including SMTA, IEEE, IMAPS and IPC developing electronic industry related standards. Vern is also a member of the IPC organizations Ambassadors Council as well as a Certified IPC Trainer for IPC-A-600 and IPC-A-610.

Current IPC standards development activity-

  • Chairman- IPC-7094, ‘Design and Assembly Process Implementation for Flip Chip and Die Size Components’
  • Co-chair- IPC-7093, ‘Design and Assembly Process Implementation for Bottom Terminal Components (SON and QFN)’.
  • Co-chair- IPC-7092, ‘Design and Assembly Process Implementation for Embedded Components’.
  • Co-chair- IPC-7091, ‘Design and Assembly Process Implementation for 3D Semiconductor Package Technology’